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contemporary Consulting-Specifying Engineer webcast presenters Tom Divine, PE, project supervisor, Smith Seckman Reid Inc., and Kenneth Kutsmeda, PE, LEED AP, Jacobs Engineering, reply reader questions on what unusual code necessities will suggest for consulting engineers.
Q: When is it required to absorb a 3 pole and four pole ATS?
Q: With recognize to breaker coordination; what are the favorite electronic trips: LI, LS/I, LSI, or LSIG?
Q: accomplish you advocate dual hot-standby manage PLCs when installing parallel gensets?
Q: Are schools regarded to subsist stage 1 or degree 2 amenities? usually, stage 1 is needed for fitness custody or mission censorious facilities handiest.
Q: what's the intent/aim of fleshly isolating the considerable department and lifestyles defense branches? Can one absorb a uncertain repercussion on the different?
Q: Is mineral-insulated (MI) cable obligatory for not obligatory standby generator feeder circuits?
Q: Does the ten-2nd vigour restoration start time apply to the main service or to the conclusion spend gadget?
Q: Does the emergency device consist of conductors and different device upstream from an ATS on the regular aspect of the ATS?
Q: should the emergency provider switchboard that feeds the ATSs subsist in a separate leeway from the leeway that contains the ATSs?
Q: If the only vital concern is egress lights, can that subsist addressed with battery lights, and if so, can my system subsist standby best?
Q: When referring to the NEC as regarding the EPSS, accomplish you deserve to additionally coincide with article 695 elevators and 517 hospitals for further requirements?
Q: How lengthy does the crank examine should subsist accomplished on the generator?
Q: Is the spend of closed transition transfer switches informed for level 1 facilities? Any concerns with the usage of closed transition switches?
Q: What are the requirements for the life security and significant offshoot programs when the constructing—specifically a talented nursing facility—has a replete pile backup generator? accomplish you still require separate ATSs, besides the fact that they absorb separate panels and wiring within the constructing? Contractors consider here's now not essential.
Q: If I even absorb a device per Article 701 and Article 702 software, what branches accomplish the battery charger, gasoline pump, and dampers secure connected to?
Q: If a sanatorium is to subsist 100% backed up with the aid of turbines, is it a violation of NEC 517.30(B)(4)-switch Switches to secure rid of any switch switches by using providing Medium Voltage generators and tie them thru a paralleling outfit to a Medium Voltage Distribution Switchgear at the significant Utility Plant? switch of vigour may subsist at the Medium Voltage switchgear.
Q: might the 517.34 outfit subsist considered as a 701 device?
Q: To verify under on-website or transportable load pecuniary institution, accomplish amenities absorb a checking out switch change to connect the weight pecuniary institution to the gadget and supply that auto removal of load pecuniary institution if utility energy fails birthright through load pecuniary institution testing?
Q: are you able to combine Article seven hundred-class masses and Article 701-classification loads in the equal switchgear and on the identical OCPD of a generator?
Q: whereas performing the two hour load verify per 7.13.four.3, I assume the generator OEM manufacturing facility can discharge only a 2 hour reactive load verify at rated power factor to coincide to 7.13.4.three.2, relevant?
– Edited by using Jessica DuBois-Maahs, affiliate content supervisor, CFE Media, jdmaahs(a)cfemedia.com.
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swiftly migrating highbrow property (IP) from one foundry to yet another and from one technique node to the next will likewise subsist a difficult, however indispensable, a Part of the business, mainly if the IP is generated and delivered as hardmacro IP. That’s as a result of tough IP or a GDSII netlist versus soft IP, RTL or gate-stage netlist ought to subsist accessible for any primary foundries and for a large altenative of technique nodes at each foundry.
Designing unusual recollection IP is essentially a manual assignment that includes greater analog circuits —cost pumps, voltage regulators and sustain amplifiers, for example — than most common sense designs. At four megabytes (Mb), the design burden dealing with the layout supervisor and his implementation crew is bold.
These considerations are habitual of reminiscence design, and the Kilopass team ran into them when designing a contemporaneous 4-Mb reminiscence IP block. Its sustain offers techniques through which other groups can overcome these challenges.
To ease the burden, the group recognized facets of the design that could subsist automated, liberating them to pay attention to essential analog elements that ought to subsist tailor-made for someone foundry and technique. The outcome is an electronic design automation (EDA) device plod developed for the newest anti-fuse non-unstable reminiscence (NVM) product line.
Exploiting the EDA device circulation
the spend of commercially purchasable EDA solutions, the primary task to subsist automated was speedy and accurate entry of design concepts, together with managing design intent in a system that flowed naturally in the schematic. This allowed designers to visualize and steal into account the numerous interdependencies of an analog or mixed-signal design and its results on circuit performance.
In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by using an additional inside team. The project of merging the current layout with the relaxation of the recollection design became a simple system requiring a day of manual vicinity and route or connecting I/Os and routing vigor and floor.
The crew made spend of the potential to embed design constraints within the netlist handed between the entrance-end design team and the implementation team. Up unless that point, those constraints had been communicated by using cryptic notes on the schematic. as an example: Specify that two gates obligatory to subsist matched or a particular internet is censorious and its optimum size requisite to no longer subsist passed within the layout. Communicated the ancient manner, when the schematic become given to the implementation engineer, the designer could simplest hope that the implementation crew achieved the favored effect.
The implementation crew built a brand unusual recollection with the aid of making a single recollection mobile then replicated it to build the more complicated arrays — a bottom-up approach versus the common right-down approach that tremendous digital SoC design groups construct spend of. The reminiscence consisted of quite cell comprising two transistors.
once the bit mobilephone was created and optimized, the telephone became replicated along a horizontal line of size n (32, for instance), as distinct in the schematic. once the line of reminiscence cells became created, it turned into replicated vertically m number of rows (32, as an example), as targeted in the schematic. during this method, the implementation engineer created a 1-Mb reminiscence array. The system was repeated three more instances to create the 4-Mb memory, a two-via-two matrix of 1-Mb arrays.
In setting up the prefatory netlist, the front-end dressmaker labeled each of the bit cells and its linked vigor, ground, bit line and note line. He then precise the number of bit cells to subsist powered by way of a given energy internet to construct inescapable that each phone obtained the equal quantity of present.
The capacity to set constraints in the netlist passed to the implementation engineer ensured the design intent became captured in closing layout.
Automating Repetitive guide projects
Automating repetitive projects tremendously decreased the time to complete the layout as neatly. for example, labeling the bit line, notice line, feel amplifier, and energy and ground for a 4-Mb reminiscence can steal appreciable time if done manually. Surrendering the assignment to the EDA device reduced the chore to a handful of keyboard operations.
In a pull-down menu, the implementation engineer achieved a contour that asked for the signal identify, variety of pins to subsist labeled, x and y coordinates of the first signal, spacing between pins, and the measurement of the text. From this counsel, the design device created each particular person signal name.
once the reminiscence IP become applied for the 40-nanometer (nm) technique at foundry A, the layout crew turned into confronted with converting the reminiscence to 40 nm at one other foundry. With the automated EDA stream, this was decreased to a two-step procedure: layer mapping followed by statistics manipulation. in the first step, the mapping table for foundry A’s forty-nm library become changed with the mapping desk for foundry B’s 40-nm library. The tool then immediately produced a layout for foundry B. The system became not absolutely automatic, as every foundry has its own exciting rules; hence exceptions that don't map one-to-one are highlighted.
The implementation engineer examined any generated exceptions then made fundamental alterations. as an instance, in foundry A, the bit phone might likewise spend layer C and D, whereas in foundry B, layer D and E are used. once the conversion changed into accomplished, a design rule examine (DRC) become performed along with remaining verification.
This automation took half the time compared with ranging from scratch, enabling rapid migration of IP from one foundry to an additional. while designing unusual recollection IP, such as Kilopass’ Gusto anti-fuse NVM, continues to subsist more often than not a guide effort, facets may likewise subsist automated, enabling the layout and implementation group to concentrate on censorious analog features that must subsist tailor-made for a person foundry and process.
creator Bio: Bernd Stamme is Director for advertising and functions at Kilopass know-how. He has more than 15 years of sustain within the IP and semiconductor industry. prior to Kilopass, he become the Director of IP know-how at SiRF technology managing the licensing and a success integration of third-celebration IP into SiRF’s GPS chip units. earlier than SiRF, he held administration positions in LSI logic’s CoreWare organization and worked on high-pace SerDes IP, communication interfaces and processor core. Stamme holds a Dipl.-Ing. degree in Electrical Engineering from FH Bielefeld in Germany.
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Rapidly migrating intellectual property (IP) from one foundry to another and from one process node to the next can subsist a challenging, but necessary, Part of the business, especially if the IP is generated and delivered as hardmacro IP. That’s because arduous IP or a GDSII netlist versus soft IP, RTL or gate-level netlist must subsist available for any major foundries and for a wide selection of process nodes at each foundry.
Designing unusual recollection IP is largely a manual task that involves more analog circuits —charge pumps, voltage regulators and sense amplifiers, for example — than most logic designs. At four megabytes (Mb), the design burden facing the layout manager and his implementation team is formidable.
These issues are typical of recollection design, and the Kilopass team ran into them when designing a recent 4-Mb recollection IP block. Its sustain offers ways in which other teams can overcome these challenges.
To ease the burden, the team identified elements of the design that could subsist automated, freeing them to concentrate on censorious analog elements that must subsist tailored for an individual foundry and process. The result is an electronic design automation (EDA) tool current developed for the latest anti-fuse non-volatile recollection (NVM) product line.
Exploiting the EDA Tool Flow
Using commercially available EDA solutions, the first task to subsist automated was rapid and accurate entry of design concepts, including managing design intent in a way that flowed naturally in the schematic. This allowed designers to visualize and understand the many interdependencies of an analog or mixed-signal design and its effects on circuit performance.
In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by another internal team. The task of merging the existing layout with the relaxation of the recollection design was a simple process requiring a day of manual region and route or connecting I/Os and routing power and ground.
The team made spend of the capacity to embed design constraints in the netlist passed between the front-end design team and the implementation team. Up until that point, those constraints were communicated by cryptic notes on the schematic. For example: Specify that two gates needed to subsist matched or a specific net is censorious and its maximum length must not subsist exceeded in the layout. Communicated the obsolete way, when the schematic was given to the implementation engineer, the designer could only hope that the implementation team achieved the desired result.
The implementation team built a unusual recollection by creating a single recollection cell then replicated it to build the more complex arrays — a bottom-up approach versus the conventional top-down approach that large digital SoC design teams employ. The recollection consisted of a bit cell comprising two transistors.
Once the bit cell was created and optimized, the cell was replicated along a horizontal line of length n (32, for example), as specified in the schematic. Once the line of recollection cells was created, it was replicated vertically m number of rows (32, for example), as specified in the schematic. In this manner, the implementation engineer created a 1-Mb recollection array. The process was repeated three more times to create the 4-Mb memory, a two-by-two matrix of 1-Mb arrays.
In developing the initial netlist, the front-end designer labeled each of the bit cells and its associated power, ground, bit line and word line. He then specified the number of bit cells to subsist powered by a given power net to ensure that each cell received the identical amount of current.
The capacity to set constraints in the netlist passed to the implementation engineer ensured the design intent was captured in final layout.
Automating Repetitive Manual Tasks
Automating repetitive tasks greatly reduced the time to complete the layout as well. For example, labeling the bit line, word line, sense amplifier, and power and ground for a 4-Mb recollection can steal considerable time if done manually. Surrendering the task to the EDA tool reduced the chore to a handful of keyboard operations.
In a pull-down menu, the implementation engineer completed a contour that asked for the signal name, number of pins to subsist labeled, x and y coordinates of the first signal, spacing between pins, and the size of the text. From this information, the design tool created each individual signal name.
Once the recollection IP was implemented for the 40-nanometer (nm) process at foundry A, the layout team was confronted with converting the recollection to 40 nm at another foundry. With the automated EDA flow, this was reduced to a two-step process: layer mapping followed by data manipulation. In the first step, the mapping table for foundry A’s 40-nm library was replaced with the mapping table for foundry B’s 40-nm library. The tool then automatically produced a layout for foundry B. The process was not completely automated, as each foundry has its own unique rules; thus exceptions that accomplish not map one-to-one are highlighted.
The implementation engineer examined any generated exceptions then made necessary adjustments. For example, in foundry A, the bit cell may spend layer C and D, whereas in foundry B, layer D and E are used. Once the conversion was completed, a design rule check (DRC) was performed along with final verification.
This automation took half the time compared with starting from scratch, enabling rapid migration of IP from one foundry to another. While designing unusual recollection IP, such as Kilopass’ Gusto anti-fuse NVM, continues to subsist mostly a manual effort, elements can subsist automated, enabling the layout and implementation team to concentrate on censorious analog elements that must subsist tailored for an individual foundry and process.
Author Bio: Bernd Stamme is Director for Marketing and Applications at Kilopass Technology. He has more than 15 years of sustain in the IP and semiconductor industry. Prior to Kilopass, he was the Director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets. Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core. Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.
One of the hardest choices encoding technicians absorb to construct is deciding between hardware and software. Hardware-based encoders and transcoders absorb had a performance edge over software since computers were invented. That's because dedicated, limited-purpose processors are designed to Run a specific algorithm, while the general-purpose processor that runs encoding software is designed to handle several functions. It's the specialist versus the jack-of-all-trades.
In the past few years, processors and workflows absorb changed. The mighty disruptor has been time and the economics of Moore's Law, which famously says that the number of transistors incorporated in a chip will approximately double every 24 months. The logical outcome of Moore's law is that the CPUs secure more powerful by a factor of two every few years, but more recently processing power seems to double every few months. Lately, Intel -- whose co-founder Gordon Moore coined Moore's Law -- has been adding specialty functions along with its math co-processors to equalize the differences between general-use processors and specialty processors.
There are many layers and elements to both a general-purpose processor and a task-specific hardware processor. The general-purpose CPU is the most common -- there are literally billions of them in any manner of computing devices -- while the more purpose-oriented processors embrace digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and integrated circuits (ICs) that are available for various industrial appliances and widely used in cellphones. Many of the structures and elements are similar across any types, but there are considerable differences. If you are not intimate with the elements of the various types, here are the basic structures of both.The General-Purpose CPU
The general-purpose CPU is laid out with resilient core elements as the arithmetic logic unit (ALU), control unit (CU), and accessory elements that present extra features for performance. Basically these two cores talk to each other, bring in recollection as needed, and ship work to the other elements. Other elements embrace I/O processors, logic gates, integrated circuits, and -- on most newer processors and especially on the Intel Xeon processors -- a beefy math co-processor. The math co-processor assists the ALU and can handle the more extreme and complex mathematical computations. Essentially, it gives the processor the extra horsepower it might require.The Dedicated Processor
Specific-purpose hardware encoders absorb been around longer than general-purpose processors, and the latter absorb been slower at mathematical equations or algorithm problems. History is vitally considerable to understand the market and technology, not to mention secure a sense of what the future holds. The earliest example of encoding was in 1965, when the Intelsat 1 (Early Bird) became the first commercial deployment of a satellite to downlink video and audio. Since then, the world has been using specific processors to process video, and the technology has made leaps and bounds to present higher density and quality.
This is a common layout of a video ARM DSP. The ARM core runs the embedded operating system, working dote a traffic cop to control input and output.
Dedicated processors -- such as dedicated signal processors (DSPs), graphics processing units (GPUs), and vector processors -- any absorb a very similar design structure. A basic and most common constituent is an I/O manager, which has a tiny onboard operating system along with memory. This is the traffic cop, controlling input and output. Then there are multiple specialized processing modules that execute the desired instructions very quickly and that DSPs and other dedicated processors support. Unlike a general-purpose processor, which has many feasible common instructions that may not subsist most efficient for the task at hand, dedicated processors rely on accelerated, per-function instructions that are more job-specific.
Dedicated processors and encoders absorb a variety of applications and workflows. If you sight at the major users of professional encoders, you will view that in many cases they rely on specialized encoders. The following well-known companies construct DSP chips: LSI Corp.; Texas Instruments, Inc.; Analog Devices, Inc.; Sony; and Magnum Semiconductor. These DSPs are used in devices such as media gateways, telepresence devices, cellphones, and military and radar processing.
FPGAs are now very well-liked implementations of DSP functions because of their flexibility of setup and upgrade. Since they are field-upgradeable, their evolution costs for the user are significantly cheaper than DSPs and application-specific integrated circuits (ASICs; more on those in a moment) from the traditional DSP providers. You can view FGPAs from Altera Corp. and Xilinx, Inc. that absorb DSP functions built in. If you want a board or system that is easier to upgrade in the field, then this is probably the best way to go.
While each manufacturer will tweak its design slightly, this is an overview of how communications and packets current into the modules of DSPs and ASICs.
Another implementation of the dedicated processor is the ASIC. These factory-programmed DSPs are used everywhere cost is a crucial consideration, because they present special functionality at optimal price and performance. In general, they are more expensive to design but are cost-effective for any appliance or board manufacturer to implement into their systems. Many manufacturers of DSPs likewise manufacture ASICs; companies such as NXP Semiconductors, Broadcom Corp., and Freescale, Inc. likewise construct custom ASIC DSPs.
If you ever open up a hardware encoding appliance -- from IP media gateways to broadcast encoder and decoders -- you will view several of the chips previously listed. You can find appliances for every industry. Today you will find a dedicated hardware-based encoding device from Harmonic, Inc.; Harris; Tandberg Data; or NTT Communications in every TV station or cable TV headend, and you'll find appliances or cards from ViewCast Corp. or Digital Rapids in many hybrid encoding farms, since they accelerate some of the functions in the hardware. If you've watched a video on YouTube, then you absorb seen video encoded by RGB Networks with the RipCode equipment, which used massive numbers of Texas Instruments, Inc. DSPs.Pros and Cons of Hardware Encoders
There are always some pros and cons when it comes to specific design hardware encoders and dedicated appliances. The dedicated hardware approach with DSPs or chips is the consummate solution for media gateways and in low latency military applications. They are designed to Run 24/7 with limited or no human interaction. There are some processors that can encode an entire frame in the 1ms-10ms (millisecond) purview and FPGAs that can encode in the 10ms-30ms range. These processes allow for the creation of appliances where the encoding latency is less than 100ms from encode to transmission to decode. birthright now you can only secure low latency using the birthright DSPs, ASICs, and FPGAs. The tolerable lifespan of an appliance is 5-10 years depending on the configuration and manufacturer. Similar lifetimes are assumed for systems that rarely change, such as satellite uplink or cable system encoders.
The primary drawback of dedicated hardware-based encoding is that the codec on the processor is generally impossible to upgrade. Every DSP, ASIC, or FPGA is based on an algorithm that was finalized years ago. By the time the chip is ready to subsist sold, the codec is 6 months to a year old. Add more design cycles for the appliance evolution and manufacturing, and the halt result is a device based on a codec that's a year or more old. If improvement to the codec comes out, the chip or device might never subsist able to integrate the unusual codec or technology due to the manufacturer or the way the chip was designed. The dedicated DSP approach can save a lot of money, but at the expense of flexibility. Those chips accomplish just what they were originally designed to accomplish and nothing more.
Video comes into a hardware encoder to a media gateway, which will construct adjustments to the video stream to address network conditions and the halt user’s video decoding device. When done, it will ship these modifications to the video decoder.
There's another issue with dedicated chip-based encoders: Who determines the trait of the codes and streams? Is it a DSP engineer, a compressionist, or the producer and director? In a TV station, it's usually a combination of chief engineer and executive producer who settle what station image goes over the air. If they spend a hardware encoder, in many cases decisions about encoding parameters absorb been taken out of their hands. The broadcast engineer has to work within the parameters the chip manufacturer has allowed halt users to change, significance that while there is usually some control, there may not subsist as much as a producer or engineer would like. There are only so many operations and cycles you can set on a chip, so some functionality is uneconomical to implement.The Pros and Cons of Software Encoders
General-purpose CPUs share some similarities and architecture with dedicated processors. They are designed to handle the everyday functions of your PC or server, and they are optimized to accomplish mundane tasks such as word processing. This is why your motherboard has a powerful graphics card in your machine; it's a specialty office that is best offloaded to a specific-designed processor. If you accomplish any nonlinear video editing, you likely absorb a capture card with some specialty processors to give you real-time output or transitions.
In the encoding and streaming industry, they mostly spend a capture board and one or more of many available software encoding packages. There are algorithms and formulas for every application, from live encoding to file-based transcoding to software-based decoding. These days most software-based encoders absorb hooks in the code to offload inescapable elements to accelerate or allow multiple CPUs to Run parallel functions to secure the best performance and quality. More recently, Intel is offering some onboard GPUs that feature decoding with MPEG, analysis of a video stream's motion vectors, and other functions.
This overview shows how a GPU or video accelerator is laid out. Again, one device works as a traffic cop to ship work to the appropriate processors, then takes the video streams back and reassembles them together, allowing video to subsist encoded at a faster rate.
Software encoders absorb allowed users to subsist much more resilient in responding to the needs of specific customers or events, and they any spend the identical general-purpose processors and capture boards to support more video formats and standards. This has been an edge for software encoders for a long time. They are smooth to reconfigure and use.
The software encoding industry has recently seen battles between open source and closed source. There are some notable pioneering closed source companies that helped drive the evolution of software encoding and streaming: Microsoft; actual Networks, Inc.; Sorenson Communications; and Adobe Systems, Inc. laid out the framework for modern streaming and web-based video. They absorb been around since the beginning, and in many cases they financed the codecs that became standards.
In addition to these pioneering companies, there has been a recent movement to open source. Some of the earlier versions such as x264 and the open source library in the University of California-Berkeley provide the foundation for most software encoders. Code is added every so often and allows others to program their custom apps. The better-known ones such as VideoLan (VLC), FFmpeg, and WebM are creating unusual versions and are catching on in common use. Some are even getting funding from some of the larger public companies. The most notable example is WebM, which is being funded mostly by Google, which made the VP8 codec open source after it acquired On2 Technologies. any this competition and activity is creating better products for consumers. The Big companies realize open source evolution and innovation is faster-moving than their own, allowing the market to grow more quickly than it otherwise might.
But software-based encoding has some drawbacks. The most considerable parameters of encoding are quality, flexibility, price, latency, and support.
Software encoding's greatest advantages over pure hardware encoders are its flexibility and quality. Software has always been able to adopt and update incredibly fast. When unusual codec optimizations Come out, encoding package updates ensue very soon after.
Software encoding can enable the producer, engineer, or other user to secure precisely the trait and image that they want, unlike the automated hardware solution, where the user has no jabber in what the overall image is and outcome will be. Some larger encoding firms hire color consultants and compressionists, along with programmers and delivery experts, any of whom assist the executive producers and directors determine what the overall outcome should sight like. It's a broadcast approach for streaming.
Later this year or in early 2013, Intel will release its Xeon Phi series of massive parallel coprocessors, which will work with existing Xeon processors and workflows.
So if software encoding wins in flexibility and quality, what about speed or latency? While some highly tuned hardware encoders present a latency down in the 30ms range, most software solutions Run in the 300ms-500ms range, if not higher. Most people who spend software encoding realize they are sacrificing some speed for quality. any that matters is whether or not they can secure the resolution and framerate they want; if it's delayed some, the workflow can subsist designed to accommodate it. On the other hand, if you require the lowest latency and fastest delivery, you will absorb to give up some quality.
Cost of support is of course an considerable issue. Will the proprietary company withhold making the version you're using, or is there a casual it will subsist withdrawn from the market? How much will the updates and upgrades cost? It turns out that upgrades in the open source community are relatively frequent, whereas upgrades in propriety software are less so.
While some people assume that open source products present lower trait or reliability than proprietary software, that's not necessarily the case. FFmpeg, VLC, and WebM are any significantly upping their quality. On the other hand, proprietary software packages such as Sorenson and MainConcept absorb likewise stood the test of time and continue to find widespread use. Interestingly, MainConcept and Sorenson are two of the few companies whose solutions are used in both software and hardware encoding; both provide codecs for the PC environment as well as specifically designed chips.Changes in Media Consumption, Changes in Media Encoding
General-purpose hardware-based decoders are now playing an considerable role in the overall media viewer world, especially as more and more viewers are quitting cable and going the IP route for any of their video consumption. Roku, Boxee, and other IP set-top boxes are DSP-based decoders. At the identical time, more and more consumers are adopting Android or iOS devices and using them as personal media players, and each device brings with it its own set of model encoding profiles and parameters. You'll find you requisite to accomplish custom scaling and probably want to present the highest feasible complexity. Then again, you requisite to spend more CPU cycles per frame, which will require more encoding time but create a better outcome.Conclusion
There will always subsist a battle between hardware encoding and software encoding. Who will win in various market segments? Why a hardware encoder versus the software encoder? Even now they are starting to view more specialty functionality appended on the general-purpose CPUs, due to the miniaturization and density of transistors and processors. For instance, Intel recently agreed to buy 190 patents and 170 patent applications from RealNetworks, and for years the company has been adding graphics processing and other accelerators or processing engines.
Dedicated hardware encoding wins in unique parallel processing situations when massive amounts of data requisite to subsist processed, as well as in low latency communications such as real-time pecuniary and some military applications. It likewise leads in situations where you want to just install the encoding tool and let it accomplish its thing, such as in situations with YouTube that can rely on automated, predefined resolutions and bitrates for a massive amount of viewers. But software encoders will subsist the tool of altenative in most applications. It's faster and cheaper to encode with software than in hardware, and once you view how the market responds to your output, it's faster and cheaper to construct modifications.
So, accomplish you most value flexibility and lower costs? Then software is probably your best bet. accomplish you requisite low latency and stream density or automated auto-transcoding for the mobile market? Then a hardware solution probably is best for you.
This article appears in the October/November, 2012, issue of Streaming Media magazine under the title "The Specialist Vs. the Jack-of-All-Trades."
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